8-bit 10-GHz 8x Time-Interleaved SAR ADC in 28-nm CMOS ID: 2019-040
An innovative ADC design achieving unprecedented efficiency and performance in digital-to-analog conversion.
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Technology Overview
This document details an 8-bit, 10-GHz, 8x time-interleaved Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) developed in 28-nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. It features a novel design with a grouped-capacitor Digital-to-Analog Converter (DAC) and a dual-path bootstrapped switch, significantly enhancing performance and reducing power consumption.
Key Advantages
- Threefold reduction in bottom-plate parasitic capacitance thanks to the grouped capacitors configured in a symmetrical comb structure
- Enhanced sampling Spurious-Free Dynamic Range (SFDR) by over 5 d
- B through the use of a dual-path bootstrapped switch
- Signal-to-Noise and Distortion Ratio (SNDR) of 36
Problems Addressed
- High power consumption in high-speed ADCs
- Nonlinear capacitance affecting signal integrity
- Limitations in achieving high precision and speed concurrently in ADC technology
Market Applications
- Semiconductor chip applications, particularly in areas requiring high-speed and high-precision data conversion
- Licensing opportunities for semiconductor manufacturers and technology developers
- Advanced research and development in digital-to-analog conversion technologies
Additional Information
Technology ID: 2019-040
Sell Sheet: Download the Sell Sheet here
Market Analysis: Contact us for a more in-depth market report
Date Published: 28 March, 2025
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